1. Field of the Invention
The present invention relates to a structure of semiconductor device and a method of manufacturing the same, and more particularly to a structure of a MOSFET that can reduce the scale of elements, increase the operation speed, and reduce the electric power consumption, and a method of manufacturing the same.
2. Description of the Background Art
FIG. 27 is a top view illustrating a structure of a general MOSFET. A channel region (not appearing in FIG. 27) is formed under a gate electrode 101, and a pair of source/drain regions 102 are formed to sandwich the channel region. Further, contact plugs 103 for connecting the source/drain regions 102 to source/drain wirings (not illustrated) are formed.
In such a MOSFET, the area of the source/drain regions 102 tend to be reduced in order to reduce the scale of elements. FIG. 28 is a top view illustrating a structure of a conventional MOSFET with reduced area of the source/drain regions. Source/drain regions 104 are formed instead of the source/drain regions 102 shown in FIG. 27. While the width of the source/drain regions in the channel length direction is L102 in the MOSFET shown in FIG. 27, the width is L104 ( less than L102) in the MOSFET shown in FIG. 28, whereby the reduction of the area of the source/drain regions is achieved.
FIG. 29 is a cross-sectional view illustrating a cross section structure with respect to the position along the line X100 shown in FIG. 28. An SOI substrate 105 has a multilayered structure in which a silicon substrate 106, a BOX (buried oxide) layer 107, and a silicon layer 108 are layered in this order. An element isolation dielectric film 109 such as STI (shallow trench isolation) is selectively formed in a top surface of the silicon layer 108.
In an element formation region of the SOI substrate 105 defined by the element isolation dielectric film 109, source/drain regions 104 forming a pair to sandwich a p-type body region 110 (corresponding to the aforesaid channel region) are formed in the top surface of the silicon layer 108. The source/drain regions 104 have an n+-type impurity diffusion region 111 formed from the top surface of the silicon layer 108 to reach the top surface of the BOX layer 107, and a silicide layer 112 formed by turning the top surface of the silicon layer 108 into silicide.
On the body region 110, a gate structure is formed having a multilayered structure in which a gate oxide film 113 and a gate electrode 101 are layered in this order. A side wall 120 made of silicon oxide is formed on the side surface of the gate structure. The gate electrode 101 has a polysilicon layer 114 formed on the gate oxide film 113 and a silicide layer 115 formed on the polysilicon layer 114.
Further, an interlayer dielectric film 118 made of silicon oxide is formed to cover the respective exposed surfaces of the silicide layers 115, 112, the side wall 120, and the element isolation dielectric film 109. Source/drain wirings 119 made of aluminum or the like are formed on the interlayer dielectric film 118. Further, contact plugs 103 for connecting the source/drain wirings 119 to the source/drain regions 104 are selectively formed in the interlayer dielectric film 118. The contact plugs 103 each have a contact hole 116 formed from the top surface of the interlayer dielectric film 118 to reach the top surface of the silicide layer 112, and a conductor plug 117 that fills the inside of the contact hole 116.
According to such a conventional MOSFET, scale reduction of elements can be achieved by reducing the area of the source/drain regions 104. Further, in a MOSFET using an ordinary bulk substrate instead of an SOI substrate, by reducing the area of the source/drain regions, the junction area between the source/drain regions and the silicon substrate having different conductivity types from each other is reduced, thereby leading to reduction of the source/drain capacitance.
However, in accordance with the reduction of the area of the source/drain regions 104, the distance between the contact plugs 103 and the gate electrode 101 becomes smaller, so that parasitic capacitance 121 generated between the two increases, thereby raising a problem.
A semiconductor device according to the first aspect of the present invention includes: an SOI substrate having a semiconductor substrate, a dielectric layer, and a semiconductor layer formed in this order; a transistor having a drain region and a source region respectively formed in the semiconductor layer, and a gate electrode formed via a gate dielectric film on a channel region sandwiched between the drain region and the source region; an interlayer dielectric film formed on the transistor; a drain wiring and a source wiring formed on the interlayer dielectric film; a first conductor formed in the interlayer dielectric film for connecting the drain wiring to the drain region; and a second conductor formed in the interlayer dielectric film for connecting the source wiring to the source region, wherein the drain region has a first part being adjacent to the channel region and a second part formed to protrude from the first part so that a part of outer peripheries of the drain region extends away from the gate electrode in a plan view, and the first conductor is connected to the second part of the drain region.
According to the first aspect of the present invention, the distance between the first conductor and the gate electrode can be increased as compared with a semiconductor device in which the first conductor is connected to the first part of the drain region. Therefore, the parasitic capacitance generated between the first conductor and the gate electrode can be reduced.
Moreover, since the SOI substrate is adopted, the drain region can be formed from the top surface of the semiconductor layer to reach the top surface of the dielectric layer. Therefore, although the area of the drain region increases by the area of the formed second part, the increase of the drain capacitance accompanying the increase of the area can be restrained to the minimum.
A semiconductor device according to the second aspect of the present invention is the semiconductor device according to the first aspect, wherein the first part of the drain region has a width of 0.2 to 0.5 xcexcm with respect to a channel length direction of the channel region, and the second part of the drain region has a length of 0.1 to 0.5 xcexcm with respect to a direction protruding from the first part of the drain region.
A semiconductor device according to the third aspect of the present invention is the semiconductor device according to the first aspect, wherein the first part of the drain region has a plurality of corner parts in a plan view, and the second part of the drain region is formed to protrude obliquely with respect to a channel width direction of the channel region from the corner part which is not adjacent to the gate electrode.
According to the third aspect of the present invention, the distance between the first conductor and the gate electrode can be increased as compared with a semiconductor device in which the second part of the drain region is formed to protrude in the channel width direction. Therefore, the parasitic capacitance generated between the two can be reduced.
A semiconductor device according to the fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein a bottom surface of the first conductor is partially in contact with the second part of the drain region by being shifted away from the gate electrode.
According to the fourth aspect of the present invention, the distance between the first conductor and the gate electrode can be further increased. Therefore, the parasitic capacitance generated between the two can be further reduced.
A semiconductor device according to the fifth aspect of the present invention is the semiconductor device according to the first aspect, wherein the source region has a first part being adjacent to the channel region and a second part formed to protrude from the first part so that a part of outer peripheries of the source region extends away from the gate electrode in a plan view, and the second conductor is connected to the second part of the source region.
According to the fifth aspect of the present invention, the distance between the second conductor and the gate electrode can be increased as compared with a semiconductor device in which the second conductor is connected to the first part of the source region. Therefore, the parasitic capacitance generated between the second conductor and the gate electrode can be reduced.
A semiconductor device according to the sixth aspect of the present invention is the semiconductor device according to the fifth aspect, wherein the first part of the source region has a width of 0.2 to 0.5 xcexcm with respect to a channel length direction of the channel region, and the second part of the source region has a length of 0.1 to 0.5 xcexcm with respect to a direction protruding from the first part of the source region.
A semiconductor device according to the seventh aspect of the present invention is the semiconductor device according to the fifth aspect, wherein the first part of the source region has a plurality of corner parts in a plan view, and the second part of the source region is formed to protrude obliquely with respect to a channel width direction of the channel region from the corner part which is not adjacent to the gate electrode.
According to the seventh aspect of the present invention, the distance between the second conductor and the gate electrode can be increased as compared with a semiconductor device in which the second part of the source region is formed to protrude in the channel width direction. Therefore, the parasitic capacitance generated between the two can be reduced.
A semiconductor device according to the eighth aspect of the present invention is the semiconductor device according to the fifth aspect, wherein a bottom surface of the second conductor is partially in contact with the second part of the source region by being shifted away from the gate electrode.
According to the eighth aspect of the present invention, the distance between the second conductor and the gate electrode can be further increased. Therefore, the parasitic capacitance generated between the two can be further reduced.
A semiconductor device according to the ninth aspect of the present invention is the semiconductor device according to the first aspect, wherein the source region has a first part being adjacent to the channel region, and the second conductor is connected to the first part of the source region.
According to the ninth aspect of the present invention, the distance between the second conductor and the gate electrode can be decreased as compared with a semiconductor device according to any one of the fifth to eighth aspects of the present invention. Therefore, rise of the source resistance caused by disposal of the second conductor away from the gate electrode can be avoided, thereby preventing generation of the substrate bias effect accompanying the rise of the source resistance.
A semiconductor device according to the tenth aspect of the present invention is the semiconductor device according to the first aspect, wherein the transistor further has a side wall formed on a side surface of the gate electrode, and the side wall is constructed with a porous material.
According to the tenth aspect of the present invention, the dielectric constant of the side wall can be reduced by forming the side wall with a porous material. Therefore, the parasitic capacitance generated between the first and second conductors and the gate electrode can be reduced as compared with a semiconductor device having a side wall made of a non-porous material.
A semiconductor device according to the eleventh aspect of the present invention is the semiconductor device according to the first aspect, wherein the interlayer dielectric film is formed except for a region between the gate electrode and the first and second conductors.
According to the eleventh aspect of the present invention, the dielectric constant of the region between the gate electrode and the first and second conductors is reduced. Therefore, the parasitic capacitance generated between the two can be reduced.
A semiconductor device according to the twelfth aspect of the present invention includes: a substrate; a transistor having a pair of source/drain regions formed in the substrate, a gate electrode formed via a gate dielectric film on a channel region sandwiched between the pair of source/drain regions, and a side wall formed on a side surface of the gate electrode; an interlayer dielectric film formed on the transistor; source/drain wirings formed on the interlayer dielectric film; and conductors formed in the interlayer dielectric film for connecting the source/drain wirings to the source/drain regions, wherein the side wall is constructed with a porous material.
According to the twelfth aspect of the present invention, the dielectric constant of the side wall can be reduced by forming the side wall with a porous material. Therefore, the parasitic capacitance generated between the conductors and the gate electrode can be reduced as compared with a semiconductor device having a side wall made of a non-porous material.
A semiconductor device according to the thirteenth aspect of the present invention includes: a substrate; a transistor having a pair of source/drain regions formed in the substrate, and a gate electrode formed via a gate dielectric film on a channel region sandwiched between the pair of source/drain regions; an interlayer dielectric film formed on the transistor; source/drain wirings formed on the interlayer dielectric film; and conductors formed in the interlayer dielectric film for connecting the source/drain wirings to the source/drain regions, wherein the interlayer dielectric film is formed except for a region between the gate electrode and the conductors.
According to the thirteenth aspect of the present invention, the dielectric constant of the region between the gate electrode and the conductors is reduced. Therefore, the parasitic capacitance generated between the two can be reduced.
A method of manufacturing a semiconductor device according to the fourteenth aspect of the present invention includes the steps of: (a) preparing a substrate; (b) forming a gate structure made of a multilayered structure having a gate dielectric film and a gate electrode formed in this order on a main surface of the substrate; (c) forming a side wall on a side surface of the gate structure; (d) forming source/drain regions by introducing an impurity into a part of the substrate where the gate structure and the side wall are not formed; (e) forming an interlayer dielectric film on a structure obtained by the step (d); (f) forming conductors in the interlayer dielectric film, the conductors being connected to the source/drain regions; (g) forming source/drain wirings on the interlayer dielectric film, the source/drain wirings being connected to the conductors; and (h) removing the interlayer dielectric film between the conductors and the gate structure.
According to the fourteenth aspect of the present invention, the dielectric constant of the region between the gate electrode and the conductors is reduced. Therefore, the parasitic capacitance generated between the two can be reduced.
A method of producing a semiconductor device according to the fifteenth aspect of the present invention is the method of producing a semiconductor device according to the fourteenth aspect, wherein the side wall is also removed in the step (h).
According to the fifteenth aspect of the present invention, the dielectric constant of the region between the gate electrode and the conductors is further reduced by removing the side wall. Therefore, the parasitic capacitance generated between the two can be further reduced.
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which the increase of the parasitic capacitance generated between the contact plugs of the source/drain regions and the gate electrode can be restrained while reducing the area of the source/drain regions. These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.